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ltc3722-1/ltc3722-2 1 372212fb for more information www.linear.com/ltc3722 typical application features description synchronous dual mode phase modulated full bridge controllers the lt c ? 3722-1/ltc3722-2 phase-shift pwm controllers provide all of the control and protection functions neces - sary to implement a high eficiency, zero voltage switched (zvs), full bridge power converter. adaptive zvs circuitry delays the turn-on signals for each mosfet independent of internal and external component tolerances. manual delay set mode enables secondary side control operation or direct control of switch turn-on delays. the ltc3722-1/ltc3722-2 feature adjustable synchron- ous rectiier timing for optimal eficiency. a uvlo p rogram input provides accurate system turn-on and turn-off voltages. the ltc3722-1 features peak current mode control with programmable slope compensation and leading edge blanking, while the ltc3722-2 employs voltage mode control. the ltc3722-1/ltc3722-2 feature extremely low operating and start-up currents. both devices include a full range of protection features and are available in the 24-pin surface mount gn package. 12v out , 240w converter ef?ciency applications n adaptive or manual delay control for zero voltage switching operation n adjustable synchronous recti?cation timing for highest ef?ciency n adjustable maximum zvs delay n adjustable system undervoltage lockout hysteresis n programmable leading edge blanking n very low start-up and quiescent currents n current mode (ltc3722-1) or voltage mode (ltc3722-2) operation n programmable slope compensation n v cc uvlo and 25ma shunt regulator n 50ma output drivers n soft-start, cycle-by-cycle current limiting and hiccup mode short-circuit protection n 5v, 15ma low dropout regulator n 24-pin surface mount gn package n telecommunications, infrastructure power systems n distributed power architectures n server power supplies l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and directsense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. c in r1 ltc3722 v in 36v to 72v ma me mf mb mc md u1 u2 u3 l1l2 rcs t1 t2 c1 v out 12v c out 372212 ta01a u1, u2: ltc4440 gate driver u3: ltc3901 gate driver current (a) 0 efficiency (%) 9590 85 80 75 16 372212 ta01b 42 6 10 14 18 8 12 20 36v in 72v in 48v in downloaded from: http:///
ltc3722-1/ltc3722-2 2 372212fb for more information www.linear.com/ltc3722 absolute maximum ratings v cc to gnd (low impedance source) ........ C0.3v to 10v (chip self regulates at 10.3v) uvlo to gnd .............................................. C0.3v to v cc all other pins to gnd (low impedance source) .......................... C0.3v to 5.5v v cc (current fed) ................................................... 25ma (note 1) pin configuration order information lead free finish tape and reel part marking package description temperature range ltc3722egn-1#pbf ltc3722egn-1#trpbf ltc3722egn-1 24-lead plastic ssop C40c to 85c ltc3722egn-2#pbf ltc3722egn-2#trpbf ltc3722egn-2 24-lead plastic ssop C40c to 85c ltc3722ign-1#pbf ltc3722ign-1#trpbf ltc3722ign-1 24-lead plastic ssop C40c to 85c ltc3722ign-2#pbf ltc3722ign-2#trpbf ltc3722ign-2 24-lead plastic ssop C40c to 85c ltc3722hgn-1#pbf ltc3722hgn-1#trpbf ltc3722hgn-1 24-lead plastic ssop C40c to 150c consult ltc marketing for parts speciied with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based inish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speciications, go to: http://www.linear.com/tapeandreel/ v ref output current ................................. self regulated outputs (a, b, c, d, e, f) current ....................... 100ma operating junction temperature range (note 6) .................................................. C40c to 150c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c ltc3722-1 ltc3722-2 12 3 4 5 6 7 8 9 1011 12 top view gn package 24-lead narrow plastic ssop 2423 22 21 20 19 18 17 16 15 14 13 sync dprg cs comp rleb fb ss nc pdly sbus adly uvlo c t gndpgnd outa outb outc v cc outdoute outf v ref sprg t jmax = 125c, ja = 100c/w 12 3 4 5 6 7 8 9 1011 12 top view gn package 24-lead narrow plastic ssop 2423 22 21 20 19 18 17 16 15 14 13 sync ramp cs comp dprg fb ss nc pdly sbus adly uvlo c t gndpgnd outa outb outc v cc outdoute outf v ref sprg t jmax = 125c, ja = 100c/w downloaded from: http:///
ltc3722-1/ltc3722-2 3 372212fb for more information www.linear.com/ltc3722 electrical characteristics symbol parameter conditions min typ max units input supplyv ccuv v cc under voltage lockout measured on v cc 10.25 10.5 v v cchy v cc uvlo hysteresis measured on v cc 3.8 4.2 v i ccst start-up current v cc = v uvlo C 0.3v ltc3722e-1/ltc3722i-1/ltc3722e-2/ltc3722i-2 ltc3722h-1 l l 145 145 230 250 a a i ccrn operating current no load on outputs 5 8 ma v shunt shunt regulator voltage current into v cc = 10ma 10.3 10.8 v r shunt shunt resistance current into v cc = 10ma to 17ma 1.1 3.5 suvlo system uvlo threshold measured on uvlo pin, 10ma into v cc 4.8 5.0 5.2 v shyst system uvlo hysteresis current current flows out of uvlo pin 8.5 10 11.5 a delay blocks dthr delay pin threshold adly and pdly sbus = 1.5v sbus = 2.25v l l 1.4 2.1 1.5 2.25 1.6 2.4 v v dhys delay hysteresis current adly and pdly sbus = 1.5v, adly/pdly = 1.7v 1.3 ma dtmo delay timeout r dprg = 60.4k 100 ns dfxt fixed delay threshold measured on sbus 4 v dftm fixed delay time sbus = v ref , adly, pdly = 1v 70 ns phase modulatori cs cs discharge current cs = 1v, comp = 0v, c t = 4v, ltc3722-1 only 50 ma i slp slope compensation current measured on cs, c t = 1v c t = 2.25v 30 68 a a dc max maximum phase shift comp = 4.5v l 95 98.5 % dc min minimum phase shift comp = 0v l 0 0.5 % oscillator osci initial accuracy t a = 25c, c t = 270pf 225 250 275 khz osct total variation v cc = 6.5v to 9.5v l 215 250 285 khz oscv c t ramp amplitude measured on c t 2.2 v osyt sync threshold measured on sync 1.6 1.9 2.2 v osyw minimum sync pulse width measured at outputs (note 2) 100 ns osyr sync frequency range measured at outputs (note 2) 1000 khz error ampli?erv fb fb input voltage comp = 2.5v (note 4) 1.172 1.204 1.236 v fbi fb input range measured on fb (note 5) C0.3 2.5 v a vol open-loop gain comp = 1v to 3v (note 4) 70 90 db iib input bias current comp = 2.5v (note 4) 5 20 na v oh output high load on comp = C100a 4.7 4.92 v v ol output low load on comp = 100a 0.18 0.4 v i source output source current comp = 2.5v 400 800 a i sink output sink current comp = 2.5v 2 5 ma the l denotes the speci?cations which apply over the speci?ed operating junction temperature range, otherwise speci?cations are at t a = 25c. v cc = 9.5v, c t = 270pf, r dprg = 60.4k, r sprg = 100k, unless otherwise noted (note 6). downloaded from: http:///
ltc3722-1/ltc3722-2 4 372212fb for more information www.linear.com/ltc3722 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: sync amplitude = 5v p-p , pulse width = 50ns. verify output (a-f) frequency = one-half sync frequency. note 3: includes leading edge blanking delay, r leb = 20k. note 4: fb is driven by a servo-loop ampliier to control v comp for these tests.note 5: set fb to C0.3v, 2.5v and insure that comp does not phase invert. note 6: the ltc3722 is tested under pulsed load condition such that t j t a . the ltc3722e-1/ltc3722e-2 are guaranteed to meet performance speciications from 0c to 85c. speciications over the C40c to 85c operating junction temperature range are assured by design, symbol parameter conditions min typ max units referencev ref initial accuracy t a = 25c, measured on v ref 4.925 5.00 5.075 v refld load regulation load on v ref = 100a to 5ma 2 15 mv refln line regulation v cc = 6.5v to 9.5v 0.9 10 mv reftv total variation line, load l 4.900 5.000 5.100 v refsc short-circuit current v ref shorted to gnd 18 30 45 ma outputs outh(x) output high voltage i out(x) = C50ma 7.9 8.4 v outl(x) output low voltage i out(x) = 50ma 0.6 1 v r hi(x) pull-up resistance i out(x) = C50ma to C10ma 22 30 r lo(x) pull-down resistance i out(x) = C50ma to C10ma 12 20 t r(x) rise time c out(x) = 50pf (note 8) 5 15 ns t f(x) fall time c out(x) = 50pf (note 8) 5 15 ns sdel sync driver turn-0ff delay r sprg = 100k 180 ns current limit and shutdown clpp pulse by pulse current limit threshold measured on cs ltc3722e-1/ltc3722i-1/ltc3722e-2/ltc3722i-2 ltc3722h-1 270 270 300 300 330 340 mv mv clsd shutdown current limit threshold measured on cs 0.55 0.65 0.73 v cldel current limit delay to output 100mv overdrive on cs (notes 3, 7) 80 ns ssi soft-start current ss = 2.5v 7 12 17 a ssr soft-start reset threshold measured on ss 0.7 0.4 0.1 v f lt fault reset threshold measured on ss 4.5 3.9 3.5 v the l denotes the speci?cations which apply over the speci?ed operating junction temperature range, otherwise speci?cations are at t a = 25c. v cc = 9.5v, c t = 270pf, r dprg = 60.4k, r sprg = 100k, unless otherwise noted (note 6). characterization and correlation with statistical process controls. the ltc3722i-1/ltc3722i-2 are guaranteed over the C40c to 85c operating junction temperature range and the ltc3722h-1 is guaranteed over the C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these speciications is determined by speciic operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 7: guaranteed by design, not tested in production. note 8: rise time is measured from the 10% to 90% points of the rising edge of the driver output signal. fall time is measured from the 90% to 10% points of the falling edge of the driver output signal. electrical characteristics downloaded from: http:///
ltc3722-1/ltc3722-2 5 372212fb for more information www.linear.com/ltc3722 typical performance characteristics leading edge blanking time vs r leb v ref vs i ref v ref vs temperature error ampli?er gain/phase start-up i cc vs temperature delay hysteresis current vs temperature start-up i cc vs v cc v cc vs i shunt oscillator frequency vs temperature v cc (v) 0 i cc (a) 100 150 8 372212 g01 50 0 2 4 6 10 200 t a = 25c i shunt (ma) 0 v cc (v) 10.00 10.25 40 372212 g02 9.759.50 10 20 30 50 10.50 t a = 25c r leb (k) 0 blank time (ns) 350300 250 200 150 100 50 0 372212 g04 40 100 20 10 30 50 70 90 60 80 t a = 25c i ref (ma) 0 v ref (v) 5.055.00 4.95 4.90 4.85 4.80 15 25 40 372212 g05 5 10 20 30 35 t a = 25c t a = 85c t a = C40c frequency (hz) gain (db) phase (deg) C180 1m 372212 g07 C270C360 10 1k 100 10k 100k 10m 100 8060 40 20 0 t a = 25c temperature (c) 230 frequency (khz) 240 250 260 C10 30 70 110 372212 g03 150 C30 C50 10 50 90 130 c t = 270pf temperature (c) C50 v ref (v) 4.99 5.00 5.01 110 372212 g06 4.98 4.97 4.96 C30 C10 10 30 50 70 90 130 150 temperature (c) C60 100 i cc (a) 110 130 140 150 60 190 372212 g08 120 0 C30 90 120 30 150 160 170 180 temperature (c) C60 hysteresis current (ma) 1.286 1.298 1.300 1.302 0 60 90 372212 g09 1.282 1.294 1.290 1.284 1.2961.280 1.292 1.288 C30 30 120 150 sbus = 1.5v downloaded from: http:///
ltc3722-1/ltc3722-2 6 372212fb for more information www.linear.com/ltc3722 typical performance characteristics fb input voltage vs temperature delay timeout vs r dprg zvs delay in fixed mode, sbus = 5v synchronous driver turn-off delay in fixed mode synchronous driver turn-off delay in adaptive mode, sbus = 1.5v slope current vs temperature v cc shunt voltage vs temperature delay pin threshold vs temperature r dprg (k) 10 0 delay (ns) 50 100 150 200 300 60 110 160 210 372212 g14 260 310 250 sbus = 1.125v sbus = 2.25v t a = 25c sbus = 1.5v r dprg (k) 10 0 delay (ns) 50 100 150 200 300 60 110 160 210 372212 g15 260 310 250 adly = pdly = 1.125v adly = pdly = 2.25v adly = pdly = 1.5v t a = 25c r sprg (k) 10 200 250 350 160 372212 g16 150 100 60 110 210 50 0 300 delay (ns) t a = 25c r sprg (k) 10 20 delay (ns) 100 140 180 260 30 110 150 372212 g17 60 220 90 190 50 70 130 170 b hi-f low a hi-e low t a = 25c temperature (c) C60 0 current (a) 10 30 40 50 60 90 372212 g10 20 0 C30 90 120 30 150 60 70 80 c t = 2.25v c t = 1v temperature (c) C60 10.2 10.3 10.5 30 90 372212 g11 10.110.0 C30 0 60 120 150 9.9 9.8 10.4 shunt voltage (v) i cc = 10ma temperature (c) C60 1.4 threshold (v) 1.5 1.7 1.8 1.9 2.42.1 0 60 90 120 372212 g12 1.6 2.2 2.32.0 C30 30 150 sbus = 2.25v sbus = 1.5v temperature (c) C60 fb voltage (v) 1.209 30 372212 g13 1.206 1.204 C30 0 60 1.2031.202 1.2101.208 1.207 1.205 90 120 150 downloaded from: http:///
ltc3722-1/ltc3722-2 7 372212fb for more information www.linear.com/ltc3722 pin functions sync (pin 1/pin 1): synchronization input/output for the oscillator. the input threshold for sync is approximately 1.9v, making it compatible with both cmos and ttl logic. terminate sync with a 5.1k resistor to gnd. dprg (pin 2/pin 5): programming input for default zero voltage transition (zvs) delay. connect a resistor from dprg to v ref to set the maximum turn on delay for outputs a, b, c, d. the nominal voltage on dprg is 2v. ramp (na/pin 2): input to phase modulator comparator for ltc3722-2 only. the voltage on ramp is internally level shifted by 650mv. cs (pin 3/pin 3): input to phase modulator for the ltc3722-1. input to pulse-by-pulse and overload current limit comparators, output of slope compensation circuitry. the pulse by pulse comparator has a nominal 300mv threshold, while the overload comparator has a nominal 650mv threshold. comp (pin 4/pin 4): error ampliier output, inverting input to phase modulator. r leb (pin 5/na): timing resistor for leading edge blank - ing. use a 10k to 100k resistor to program from 40ns to 310ns of leading edge blanking of the current sense signal on cs for the ltc3722-1. a 1% tolerance resistor is recommended. the ltc3722-2 has a ixed blanking time of approximately 80ns. fb (pin 6/pin 6): error ampliier inverting input. this is the voltage feedback input for the ltc3722. the nominal regulation voltage at fb is 1.204v. ss (pin 7/pin 7): soft-start/restart delay circuitry timing capacitor. a capacitor from ss to gnd provides a controlled ramp of the current command (ltc3722-1), or duty cycle (ltc3722-2). during overload conditions ss is discharged to ground initiating a soft-start cycle. nc (pin 8/pin 8): no connection. tie this pin to gnd. pdly (pin 9/pin 9): passive leg delay circuit input. pdly is connected through a voltage divider to the left leg of the bridge in adaptive zvs mode. in ixed zvs mode, a voltage between 0v and 2.5v on pdly, programs a ixed zvs delay time for the passive leg transition. sbus (pin 10/pin 10): line voltage sense input. sbus is connected to the main dc voltage feed by a resistive volt - age divider when using adaptive zvs control. the voltage divider is designed to produce 1.5v on sbus at nominal v in . if sbus is tied to v ref , the ltc3722-1/ltc3722-2 is conigured for ixed mode zvs control. adly (pin 11/pin 11): active leg delay circuit input. adly is connected through a voltage divider to the right leg of the bridge in adaptive zvs mode. in ixed zvs mode, a voltage between 0v and 2.5v on adly, programs a ixed zvs delay time for the active leg transition. uvlo (pin 12/pin 12): input to program system turn- on and turn-off voltages. the nominal threshold of the uvlo comparator is 5v. uvlo is connected to the main dc system feed through a resistor divider. when the uvlo threshold is exceeded, the ltc3722-1/ltc3722-2 commences a soft-start cycle and a 10a (nominal) cur - rent is fed out of uvlo to program the desired amount of system hysteresis. the hysteresis level can be adjusted by changing the resistance of the divider. sprg (pin 13/pin 13): a resistor is connected between sprg and gnd to set the turn-off delay for the synchronous rectiier driver outputs (oute and outf). the nominal voltage on sprg is 2v. v ref (pin 14/pin 14): output of the 5v reference. v ref is capable of supplying up to 18ma to external circuitry. v ref should be decoupled to gnd with a 1f ceramic capacitor. outf (pin 15/pin 15): 50ma driver for synchronous rectiier associated with outb and outc. oute (pin 16/pin 16): 50ma driver for synchronous rectiier associated with outa and outd. outd (pin 17/pin 17): 50ma driver for low side of the full bridge active leg.v cc (pin 18/pin 18): supply voltage input to the ltc3722-1/ltc3722-2 and 10.25v shunt regulator. the chip is enabled after v cc has risen high enough to allow the v cc shunt regulator to conduct current and the uvlo comparator threshold is exceeded. once the v cc shunt regulator has turned on, v cc can drop to as low as 6v (typ) and maintain operation. (ltc3722-1/ltc3722-2) downloaded from: http:///
ltc3722-1/ltc3722-2 8 372212fb for more information www.linear.com/ltc3722 block diagram pin functions (ltc3722-1/ltc3722-2) outc (pin 19/pin 19): 50ma driver for high side of the full bridge active leg.outb (pin 20/pin 20): 50ma driver for low side of the full bridge passive leg. outa (pin 21/pin 21): 50ma driver for high side of the full bridge passive leg. pgnd (pin 22/pin 22): power ground for the ltc3722. the output drivers of the ltc3722 are referenced to pgnd. connect the ceramic v cc bypass capacitor di- rectly to pgnd. gnd (pin 23/pin 23): all circuits other than the output drivers in the ltc3722 are referenced to gnd. use of a ground plane is recommended but not absolutely neces - sary. c t (pin 24/pin 24): timing capacitor for the oscillator. use a 5% or better low esr ceramic capacitor for best results. ltc3722-1 current mode sync phase-shift pwm oute outf outc outd adly pgnd pdly outa outb 372212 bd01 C + C + C + C + C + 3 7 6 18 12 14 17 11 22 19 15 16 20 9 21 24 23 1 13 10 2 4 5 v cc uvlo 10.25v = on 6v = off 5v ref and ldo 1.2v ref good fault logic shutdown current limit pulse by pulse current limit 650mv slope compensation c t /r blank sscs r leb qbq r s qb r s r2 14.9k m1 20 v ref 1.2v 5v + C 650mv r1 50k phase modulator error amplifier fb comp 12a 300mv v cc good 1 = enable0 = disable osc active delay sync rectifier drivelogic passive delay qb q t v cc uvlo v ref c t sync sprg sbus dprg gnd system uvlo m2 downloaded from: http:///
ltc3722-1/ltc3722-2 9 372212fb for more information www.linear.com/ltc3722 block diagram ltc3722-2 voltage mode sync phase-shift pwm oute outf outc outd adly pgnd pdly outa outb 372212 bd02 C + C + C + C + C + 3 7 6 18 12 14 17 11 22 19 15 16 20 9 21 24 23 1 13 10 5 4 v cc uvlo 10.25v = on 6v = off 5v ref and ldo 1.2v ref good fault logic shutdown current limit pulse by pulse current limit 650mv blank ss 2 ramp cs qbq r s qb r s v ref 1.2v 5v + C 650mv r1 50k phase modulator error amplifier fb comp 12a 300mv v cc good 1 = enable0 = disable osc active delay sync rectifier drivelogic passive delay qb q t v cc uvlo v ref c t sync sprg sbus dprg gnd system uvlo m2 downloaded from: http:///
ltc3722-1/ltc3722-2 10 372212fb for more information www.linear.com/ltc3722 operation phase-shift full bridge pwm c onventional full bridge switching power supply topologies are often employed for high power, isolated dc/dc and off-line converters. although they require two additional switching elements, substantially greater power and higher eficiency can be attained for a given transformer size compared to the more common single-ended forward and lyback converters. these improvements are realized since the full bridge converter delivers power during both parts of the switching cycle, reducing transformer core loss and lowering voltage and current stresses. the full bridge converter also provides inherent automatic transformer lux reset and balancing due to its bidirectional drive coniguration. as a result, the maximum duty cycle range is extended, further improving eficiency. soft-switching variations on the full bridge topology have been proposed to improve and extend its performance and application. these zero voltage switching (zvs) techniques exploit the generally undesirable parasitic elements present within the power stage. the parasitic elements are utilized to drive near lossless switching transitions for all of the external power mosfets. ltc3722-1/ltc3722-2 phase-shift pwm controllers pro - vide enhanced performance and simplify the design task required for a zvs phase-shifted full bridge converter. the primary attributes of the ltc3722-1/ltc3722-2 as compared to currently available solutions include: 1. truly adaptive and accurate (directsense tm technology) zvs with programmable timeout. beneit: higher eficiency, higher duty cycle capability, eliminates external trim. 2. fixed zvs capability. beneit: enables secondary-side control and simpliies external circuit. timing diagram comp comp sync turn off delay (programmable) sync turn off delay (programmable) passive leg delay active leg delay outa outboutc outd rampcomp oute outf 372212 td01 note: shaded areas correspond to power delivery pulses. downloaded from: http:///
ltc3722-1/ltc3722-2 11 372212fb for more information www.linear.com/ltc3722 3 internally generated drive signals with programmable turn-off for current doubler synchronous rectiiers. beneit: eliminates external glue logic, drivers, optimal timing for highest eficiency. 4. programmable (single resistor) leading edge blanking. beneit: prevents spurious operation, reduces external iltering required on cs. 5. programmable (single resistor) slope compensation. beneit: eliminates external glue circuitry. 6. optimized current mode control architecture. beneit: eliminates glue circuitry, less overshoot at start-up, faster recovery from system faults. 7. programmable system undervoltage lockout and hys- teresis. beneit: provides an accurate turn-on voltage for power supply and reduces external circuitry. as a result, the ltc3722-1/ltc3722-2 makes the zvs topol - ogy feasible for a wider variety of applications, including those at lower power levels. the ltc3722-1/ltc3722-2 control four external power switches in a full bridge arrangement. the load on the bridge is the primary winding of a power transformer. the diagonal switches in the bridge connect the primary wind - ing between the input voltage and ground every oscillator cycle. the pair of switches that conduct are alternated by an internal lip-lop in the ltc3722-1/ltc3722-2. thus, the voltage applied to the primary is reversed in polarity on every switching cycle and each output drive signal is one-half the frequency of the oscillator. the on-time of each driver signal is slightly less than 50%. the on-time overlap of the diagonal switch pairs is controlled by the ltc3722-1/ltc3722-2 phase modulation circuitry (refer to the block and timing diagrams). this overlap sets the approximate duty cycle of the converter. the ltc3722-1/ ltc3722-2 driver output signals (outa to outf) are optimized for interface with an external gate driver ic or buffer. external power mosfets a and c require high side driver circuitry, while b and d are ground referenced and e and f are ground referenced but on the secondary-side of the isolation barrier. methods for providing drive to these elements are detailed in this data sheet. the secondary voltage of the transformer is the primary voltage divided by the transformer turns ratio. similar to a buck converter, the secondary square wave is applied to an output ilter inductor and capacitor to produce a well regulated dc output voltage. switching transitions the phase-shifted full bridge can be described by four primary operating states. the key to understanding how zvs occurs is revealed by examining the states in detail. each full cycle of the transformer has two distinct periods in which power is delivered to the output, and two free - wheeling periods. the two sides of the external bridge have fundamentally different operating characteristics that become important when designing for zvs over a wide load current range. the left bridge leg is referred to as the passive leg, while the right leg is referred to as the active leg. the following descriptions provide insight as to why these differences exist. state 1 (power pulse 1) as shown in figure 1, state 1 begins with ma, md and mf on and mb, mc and me off. during the simultane - ous conduction of ma and md, the full input voltage is applied across the transformer primary winding and fol - lowing the dot convention, v in /n is applied to the left side of lo1 allowing current to increase in lo1. the primary current during this period is approximately equal to the output inductor current (lo1) divided by the transformer turns ratio plus the transformer magnetizing current (v in ? t on )/(l mag ? 2). md turns off and me turns on at the end of state 1. state 2 (active transition and freewheel interval) md turns off when the phase modulator comparator transi - tions. at this instant, the voltage on the md/mc junction begins to rise towards the applied input voltage (v in ). the transformers magnetizing current and the relected output inductor current propels this action. the slew rate is limited by mosfet mc and mds outputcapacitance (c oss ), snubbing capacitance and the transformer inter - winding capacitance. the voltage transition on the active leg from the ground reference point to v in will always operation downloaded from: http:///
ltc3722-1/ltc3722-2 12 372212fb for more information www.linear.com/ltc3722 operation state 1 power pulse 1 v in mamb mf mcmd me mf me mf me freewheel interval mamb mcmd state 2 active transition mamb mcmd state 3 passive transition mamb mcmd state 4 power pulse 2 mamb mcmd load load load v out v out l01l02 n:1 primary and secondary shorted v out 372212 f01 i p ? i l01 / n + (v in ? t on )/ l mag + + downloaded from: http:///
ltc3722-1/ltc3722-2 13 372212fb for more information www.linear.com/ltc3722 occur, independent of load current as long as energy in the transformers magnetizing and leakage inductance is greater than the capacitive energy. that is, 1/2 ? (lm + li) ? im2 > 1/2 ? 2 ? coss ? v in 2 the worst case occurs when the load current is zero. this condition is usually easy to meet. the magnetizing current is virtually constant during this transition because the magnetizing inductance has positive voltage applied across it throughout the low to high transition. since the leg is actively driven by this current source, it is called the active or linear transition. when the voltage on the active leg has risen to v in , mosfet mc is switched on by the zvs circuitry. the primary current now lows through the two high side mosfets (ma and mc). the transformers secondary windings are electrically shorted at this time since both me and mf are on. as long as positive current lows in lo1 and lo2, the transformer primary (magnetizing) inductance is also shorted through normal transformer action. ma and mf turn off at the end of state 2. state 3 (passive transition) ma turns off when the oscillator timing period ends, i.e., the clock pulse toggles the internal lip-lop. at the instant ma turns off, the voltage on the ma/mb junction begins to decay towards the lower supply (gnd). the energy available to drive this transition is limited to the primary leakage inductance and added commutating inductance which have (i mag + i out /2n) lowing through them initially. the magnetizing and output inductors do not contribute any energy because they are effectively shorted as mentioned previously, signiicantly reducing the available energy. this is the major difference between the active and passive transitions. if the energy stored in the leakage and com - mutating inductance is greater than the capacitive energy, the transition will be completed successfully. during the transition, an increasing reverse voltage is applied to the leakage and commutating inductances, helping the overall primary current to decay. the inductive energy is thus resonantly transferred to the capacitive elements, hence, the term passive or resonant transition. assuming there is suficient inductive energy to propel the bridge leg to gnd, the time required will be approximately equal to: 2 lc when the voltage on the passive leg nears gnd, mosfet mb is commanded on by the zvs circuitry. current continues to increase in the leakage and external series inductance which is opposite in polarity to the relected output inductor current. when this current is equal in magnitude to the relected output current, the primary current reverses direction, the opposite secondary winding becomes forward biased and a new power pulse is initi - ated. the time required for the current reversal reduces the effective maximum duty cycle and must be considered when computing the power transformer turns ratio. if zvs is required over the entire range of loads, a small commutating inductor is added in series with the primary to aid with the passive leg transition, since the leakage inductance alone is usually not suficient and predictable enough to guarantee zvs over the full load range. state 4 (power pulse 2) during power pulse 2, current builds up in the primary winding in the opposite direction as power pulse 1. the primary current consists of relected output inductor cur - rent and current due to the primary magnetizing inductance. at the end of state 4, mosfet mc turns off and an active transition, essentially similar to state 2 but opposite in direction (high to low), takes place. zero voltage switching (zvs) a lossless switching transition requires that the respective full bridge mosfets be switched to the on state at the exact instant their drain-to-source voltage is zero. delaying the turn-on results in lower eficiency due to circulating cur - rent lowing in the body diode of the primary side mosfet rather than its low resistance channel. premature turn-on produces hard switching of the mosfets, increasing noise and power dissipation. ltc3722-1/ltc3722-2 adaptive delay circuitry the ltc3722-1/ltc3722-2 monitors both the input supply and instantaneous bridge leg voltages, and commands a switching transition when the expected zero voltage condition is reached. directsense technology provides optimal turn-on delay timing, regardless of input voltage, output load, or component tolerances. the directsense technique requires only a simple voltage divider sense operation downloaded from: http:///
ltc3722-1/ltc3722-2 14 372212fb for more information www.linear.com/ltc3722 network to implement. if there is not enough energy to fully commutate the bridge leg to a zvs condition, the ltc3722-1/ltc3722-2 automatically overrides the di - rectsense circuitry and forces a transition. the override or default delay time is programmed with a resistor from dprg to v ref . adaptive mode the ltc3722-1/ltc3722-2 are conigured for adaptive delay sensing with three pins, adly, pdly and sbus. adly and pdly sense the active and passive delay legs respectively via a voltage divider network, as shown in figure 2. delays exist between the time at which the ltc3722-1/ ltc3722-2 controller output transitions, to the time at which the power mosfet switches on due to mosfet turn-on delay and external driver circuit delay. ideally, we want the power mosfet to switch at the instant there is zero volts across it. by setting a threshold voltage for adly and pdly corresponding to several volts across the mosfet, the ltc3722-1/ltc3722-2 can anticipate a zero voltage vds and signal the external driver and switch to turn-on. the amount of anticipation can be tailored for any application by modifying the upper divider resistor(s). the ltc3722-1/ltc3722-2 directsense circuitry sources a trimmed current out of pdly and adly (proportional to sbus) after a low to high level transition occurs. this provides hysteresis and noise immunity for the pdly and adly circuitry, and sets the high to low threshold on adly or pdly to nearly the same level as the low to high threshold, thereby making the upper and lower mosfet vds switch points virtually identical, independent of v in . example: v in = 48v nominal (36v to 72v) 1. set up sbus: 1.5v is desired on sbus with v in = 48v. set divider current to 100a. r1 = 1.5v 100a = 15k r2 = 48v ? 1.5v 100a = 465k an optional small capacitor (0.001f) can be added across r1 to decouple noise from this input. 2. set up adly and pdly: 7v of anticipation is desired in this circuit to account for the delays of the external mosfet driver and gate drive components. r3, r4 = 1k, sets a nominal 1.5ma in the divider chain at the threshold. r5, r6 = (48v ? 7v ? 1.5v) 1.5ma = 26.3k, use (2) equal 13k segments. operation the threshold voltage on pdly and adly for both the ris - ing and falling transitions is set by the voltage on sbus. a buffered version of this voltage is used as the threshold level for the internal directsense circuitry. at nominal v in , the voltage on sbus is set to 1.5v by an external voltage divider between v in and gnd, making this voltage directly proportional to v in . the ltc3722-1/ltc3722-2 directsense circuitry uses this characteristic to zero voltage switch all of the external power mosfets, independent of input voltage. adly and pdly are connected through voltage dividers to the active and passive bridge legs respectively. the lower resistor in the divider is set to 1k. the upper resistor in the divider is selected for the desired positive transition trip threshold. to set up the adly and pdly resistors, irst determine at what drain to source voltage to turn-on the mosfets. finite sbus adly pdly r2 r5 r6 r1 r31k r41k r cs a b c d v in 372212 f02 figure 2. adaptive mode downloaded from: http:///
ltc3722-1/ltc3722-2 15 372212fb for more information www.linear.com/ltc3722 fixed delay mode the ltc3722-1/ltc3722-2 provides the lexibility through the sbus pin to disable the directsense delay circuitry and enable ixed zvs delays. the level of ixed zvs delay is proportional to the voltage programmed through the voltage divider on the pdly and adly pins (see figure 3 for more detail). programming adaptive delay time-out the ltc3722-1/ltc3722-2 controllers include a feature to program the maximum time delay before a bridge switch turn on command is summoned. this function will come into play if there is not enough energy to commutate a bridge leg to the opposite supply rail, therefore bypass - ing the adaptive delay circuitry. the time delay can be set with an external resistor connected between dprg and v ref (see figure 4). the nominal regulated voltage on dprg is 2v. the external resistor programs a current which lows into dprg. the delay can be adjusted from approximately 35ns to 300ns, depending on the resistor value. if dprg is left open, the delay time is approximately 400ns. the amount of delay can also be modulated based on an external current source that feeds current into dprg. care must be taken to limit the current fed into dprg to 350a or less. powering the ltc3722-1/ltc3722-2 the ltc3722-1/ltc3722-2 utilize an integrated v cc shunt regulator to serve the dual purposes of limiting the volt - age applied to v cc as well as signaling that the chips bias voltage is suficient to begin switching operation (under - voltage lockout). with its typical 10.2v turn-on voltage and 4.2v uvlo hysteresis, the ltc3722-1/ltc3722-2 is tolerant of loosely regulated input sources such as an auxiliary transformer winding. the v cc shunt is capable of sinking up to 25ma of externally applied current. the uvlo turn-on and turn-off thresholds are derived from an internally trimmed reference making them extremely accurate. in addition, the ltc3722-1/ltc3722-2 exhibits very low (145a typ) start-up current that allows the use of 1/8w to 1/4w trickle charge start-up resistors. the trickle charge resistor should be selected as follows: r start(max) = v in(min) ? 10.7v 250a adding a small safety margin and choosing standard values yields: application v in range r start dc/dc 36v to 72v 100k off-line 85v to 270v rms 430k pfc preregulator 390v dc 1.4m v cc should be bypassed with a 0.1f to 1f multilayer ceramic capacitor to decouple the fast transient currents demanded by the output drivers and a bulk tantalum or electrolytic capacitor to hold up the v cc supply before the bootstrap winding, or an auxiliary regulator circuit takes over. c holdup = (i cc + i drive ) ? t delay 3.8v (minimum uvlo hysteresis) operation figure 3. setup for fixed zvs delays adly pdly v ref sbus 372212 f03 r1r2 r3 figure 4. delay timeout circuitry C + turn-on output sbus + C v 2v v ref dprg r dprg 372212 f04 downloaded from: http:///
ltc3722-1/ltc3722-2 16 372212fb for more information www.linear.com/ltc3722 regulated bias supplies as low as 7v can be utilized to provide bias to the ltc3722-1/ltc3722-2. figure 5 shows various bias supply conigurations. programming undervoltage lockout th e ltc3722-1/ltc3722-2 provides undervoltage lockout (uvlo) control for the input dc voltage feed to the power converter in addition to the v cc uvlo function described in the preceding section. input dc feed uvlo is provided with the uvlo pin. a comparator on uvlo compares a divided down input dc feed voltage to the 5v precision reference. when the 5v level is exceeded on uvlo, the ss pin is released and output switching commences. at the same time a 10a current is enabled which lows out of uvlo into the voltage divider connected to uvlo. the amount of dc feed hysteresis provided by this current is: 10a ? r top , see figure 6. the system uvlo threshold is: 5v ? [(r top + r bottom )/r bottom ]. if the voltage applied to uvlo is present and greater than 5v prior to the v cc uvlo circuitry activation, then the internal uvlo logic will prevent output switching until the following three conditions are met: (1) v cc uvlo is enabled, (2) v ref is in regulation and (3) uvlo pin is greater than 5v. uvlo can also be used to enable and disable the power converter. an open drain transistor connected to uvlo, as shown in figure 6, provides this capability. off-line bias supply generation if a regulated bias supply is not available to provide v cc voltage to the ltc3722-1/ltc3722-2 and supporting circuitry, one must be generated. since the power require - ment is small, approximately 1w, and the regulation is not critical, a simple open-loop method is usually the easiest and lowest cost approach. one method that works well is to add a winding to the main power transformer, and post regulate the resultant square wave with an l-c ilter (see figure 7a). the advantage of this approach is that it maintains decent regulation as the supply voltage varies, and it does not require full safety isolation from the input winding of the transformer. some manufacturers include a primary winding for this purpose in their standard product offerings as well. a different approach is to add a winding to the output inductor and peak detect and ilter the square wave signal (see figure 7b). the polarity of this winding operation figure 5. bias con?gurations 372212 f05 12v 10% 1.5k v cc v in v cc c hold 1n52263v 0.1f 0.1f v bias < v uvlo r start 1n914 + figure 7a. auxiliary winding bias supply 372212 f07a + v cc v in c hold 0.1f r start 2k 15v* *optional 372212 f07b v cc v out v in c hold r start + 0.1f l out iso barrier on off r bottom r top uvlo 372212 f06 figure 7b. output inductor bias supply figure 6. system uvlo setup downloaded from: http:///
ltc3722-1/ltc3722-2 17 372212fb for more information www.linear.com/ltc3722 is designed so that the positive voltage square wave is produced while the output inductor is freewheeling. an advantage of this technique over the previous is that it does not require a separate ilter inductor and since the voltage is derived from the well regulated output voltage, it is also well controlled. one disadvantage is that this wind - i ng will require the same safety isolation that is required for the main transformer. another disadvantage is that a much larger v cc ilter capacitor is needed, since it does not generate a voltage as the output is irst starting up, or during short-circuit conditions. programming the ltc3722-1/ltc3722-2 oscillator the high accuracy ltc3722-1/ltc3722-2 oscillator circuit provides lexibility to program the switching frequency, slope compensation, and synchronization with minimal external components. the ltc3722-1/ltc3722-2 oscillator circuitry produces a 2.2v peak-to-peak amplitude ramp waveform on c t and a narrow pulse on sync that can be used to synchronize other pwm chips. typical maximum duty cycles of 98.5% are obtained at 300khz and 96% at 1mhz. a compensating slope current is derived from the oscillator ramp waveform and sourced out of cs. the desired amount of slope compensation is selected with single external resistor. a capacitor to gnd on c t programs the switching frequency. the c t ramp discharge current is internally set to a high value (>10ma). the dedi - cated sync i/o pin easily achieves synchronization. the ltc3722-1/ltc3722-2 can be set up to either synchronize o ther pwm chips or be synchronized by another chip or external clock source. the 1.8v sync threshold allows the ltc3722-1/ltc3722-2 to be synchronized directly from all standard 3v and 5v logic families. design procedure: 1. choose c t for the desired oscillator frequency. the switching frequency selected must be consistent with the power magnetics and output power level. in general, increasing the switching frequency will decrease the maximum achievable output power, due to limitations of maximum duty cycle imposed by transformer core reset and zvs. remember that the tranformer fre- quency is one-half that of the oscillator. c t = 1 (13.4 k ? f osc ) example: desired f osc = 330khz c t = 1/(13.4k ? f osc ) = 226pf, choose closest standard value of 220pf. a 5% or better tolerance multilayer npo or x7r ceramic capacitor is recommended for best performance. 2. the ltc3722-1/ltc3722-2 can either synchronize other pwms, or be synchronized to an external frequency source or pwm chip (see figure 8 for details). operation figure 8a. sync output (master mode) figure 8b. sync input from an external source ltc3722 ltc3722 ltc3722 c t c t c t c t c t c t sync sync sync 5.1k 5.1k 5.1k 1k1k ?? ? up to 5 slaves slaves master c t of slave(s) is 1.25 c t of master. 372212 f08a ltc3722 c t c t sync 5.1k 1k 372212 f08b external frequency source amplitude > 1.8v 100ns < pw < 0.4/ ? downloaded from: http:///
ltc3722-1/ltc3722-2 18 372212fb for more information www.linear.com/ltc3722 3. slope compensation is required for most peak current mode controllers in order to prevent subharmonic oscillation of the current control loop. in general, if the system duty cycle exceeds 50% in a ixed frequency, continuous current mode converter, an unstable con - dition exists within the current control loop. any perturbation in the current signal is ampliied by the pwm modulator resulting in an unstable condition. some common manifestations of this include alternate pulse nonuniformity and pulse width jitter. fortunately, this can be addressed by adding a corrective slope to the current sense signal or by subtracting the same slope from the current command signal (error am - pliier output). in theory, the current doubler output coniguration does not require slope compensation since the output inductor duty cycles only approach 50%. however, transient conditions can momentarily cause higher duty cycles and therefore, the possibility for unstable operation. the exact amount of required slope compensation is easily programmed by the ltc3722-1/ltc3722-2 with the addition of a single external resistor (see figure 9). the ltc3722-1/ltc3722-2 generates a current that is proportional to the instantaneous voltage on c t , (33a/v(c t )). thus, at the peak of c t , this current is approximately 74a and is output from the cs pin. a resistor connected between cs and the external current sense resistor sums in the required amount of slope compensation. the value of this resistor is dependent on several factors including minimum v in , v out , switch - ing frequency, current sense resistor value and output inductor value. an illustrative example with the design equation for current doubler secondary follows. example: v in = 36v to 72v v out = 3.3v i out = 40a l = 2.2h transformer turns ratio (n) = v in(min) ? dc max (2 ? v out ) = 5 r cs = 0.05 f sw = 300khz, i.e., transformer f = f sw 2 = 150khz r slope = v o ? r cs (2 ? l ? f sw ? 74a ? n) = 3.3v ? 0.05 2 ? 2.2h ? 300k ? 74a ? 5 r slope = 338, choose the next higher standard value to account for tolerances in i slope , r cs , n and l. operation figure 9. slope compensation circuitry bridgecurrent current sense waveform v(c t ) 33k i = cs c t 33k added slope r slope r cs 372212 f09 ltc3722 downloaded from: http:///
ltc3722-1/ltc3722-2 19 372212fb for more information www.linear.com/ltc3722 current sensing and overcurrent protectioncu rrent sensing provides feedback for the current mode control loop and protection from overload conditions. the ltc3722-1/ltc3722-2 are compatible with either resis - tive sensing or current transformer methods. internally connected to the ltc3722-1/ltc3722-2 cs pin are two comparators that provide pulse-by-pulse and overcurrent shutdown functions respectively (see figure 10). the pulse-by-pulse comparator has a 300mv nominal threshold. if the 300mv threshold is exceeded, the pwm cycle is terminated. the overcurrent comparator is set approximately 2x higher than the pulse-by-pulse level. if the current signal exceeds this level, the pwm cycle is terminated, the soft-start capacitor is quickly discharged and a soft-start cycle is initiated. if the overcurrent condition persists, the ltc3722-1/ltc3722-2 halts pwm operation and waits for the soft-start capacitor to charge up to ap - proximately 4v before a retry is allowed. the soft-start capacitor is charged by an internal 12a current source. if the fault condition has not cleared when soft-start reaches 4v, the soft-start pin is again discharged and a new cycle is initiated. this is referred to as hiccup mode operation. in normal operation and under most abnormal conditions, the pulse-by-pulse comparator is fast enough to prevent hiccup mode operation. in severe cases, how - ever, with high input voltage, very low r ds(on) mosfets and a shorted output, or with saturating magnetics, the overcurrent comparator provides a means of protecting the power converter. leading edge blanking the ltc3722-1/ltc3722-2 provides programmable leading edge blanking to prevent nuisance tripping of the current sense circuitry. leading edge blanking relieves the ilter - ing requirements for the cs pin, greatly improving the response to real overcurrent conditions. it also allows the use of a ground referenced current sense resistor or transformer(s), further simplifying the design. with a single 10k to 100k resistor from r leb to gnd, blanking times of approximately 40ns to 320ns are programmed. if not required, connecting r leb to v ref can disable leading edge blanking. keep in mind that the use of leading edge blanking will set a minimum linear control range for the phase modulation circuitry. resistive sensing a resistor connected between input common and the sources of mb and md is the simplest method of current sensing for the full bridge converter. this is the preferred method for low to moderate power levels. the sense resistor should be chosen such that the maximum rated operation figure 10. current sense/fault circuitry detail + ? + ? overload current limit 300mv650mv mod uvlo enable uvlo enable r s q r s q q q s q pwm logic h = shutdown outputs cs r cs + ? + ? c ss ss 0.4v 4.1v 12a 372212 f10 pulse by pulse current limit pwm latch blank downloaded from: http:///
ltc3722-1/ltc3722-2 20 372212fb for more information www.linear.com/ltc3722 output current for the converter can be delivered at the lowest expected v in . use the following formula to calculate the optimal value for r cs . i p equation valid for current doubler secondary. ltc3722-1: r cs = 300m v C (82.5a ? r slope ) i p (peak) i p (peak) = i o(max) 2 ? n ? eff + v in(max) ? d min l mag ? f clk ? 2 + v o (1C d min ) l out ? f clk ? n where : n = transformer turns ratio = n p n s ltc3722-2: r cs = 300mv i p (peak) current transformer sensing a current sense transformer can be used in lieu of resistive sensing with the ltc3722-1/ltc3722-2. current sense transformers are available in many styles from several manufacturers. a typical sense transformer for this ap - plication will use a 1:50 turns ratio (n), so that the sense resistor value is n times larger, and the secondary current n times smaller than in the resistive sense case. therefore, the sense resistor power loss is about n times less with the transformer method, neglecting the transformers core and copper losses. the disadvantages of this approach include, higher cost and complexity, lower accuracy, core reset/maximum duty cycle limitations and lower speed. nevertheless, for very high power applications, this method is preferred. the sense transformer primary is placed in the same location as the ground referenced sense resistor, or between the upper mosfet drains in the (ma, mc) and v in . the advantage of the high side location is a greater im-munity to leading edge noise spikes, since gate charge current and relected rectiier recovery current are largely eliminated. figure 11 illustrates a typical current sense transformer based sensing scheme. r s in this case is calculated the same as in the resistive case, only its value is increased by the sense transformer turns ratio. at high duty cycles, it may become dificult or impossible to re - set the current transformer. this is because the required transformer reset voltage increases as the available time for reset decreases to equalize the (volt ? seconds) applied. the interwinding capacitance and secondary inductance of the current sense transformer form a resonant circuit that limits the dv/dt on the secondary of the cs transformer. this, in turn, limits the maximum achievable duty cycle for the cs transformer. attempts to operate beyond this limit will cause the transformer core to walk and eventually saturate, opening up the current feedback loop. common methods to address this limitation include: 1. reducing the maximum duty cycle by lowering the power transformer turns ratio. 2. reducing the switching frequency of the converter. 3. employ external active reset circuitry. 4. using two cs transformers summed together. 5. choose a cs transformer optimized for high frequency applications. operation figure 11. current transformer sense circuitry optional filtering n:1 mb source mdsource currenttransformer r slope ramp cs r s 372212 f11 downloaded from: http:///
ltc3722-1/ltc3722-2 21 372212fb for more information www.linear.com/ltc3722 phase modulator (ltc3722-1) the ltc3722-1 phase modulation control circuitry is comprised of the phase modulation comparator and logic, the error ampliier, and the soft-start ampliier (see figure 12). together, these elements develop the required phase overlap (duty cycle) required to keep the output voltage in regulation. in isolated applications, the sensed output voltage error signal is fed back to comp across the input to output isolation boundary by an optical coupler and shunt reference/error ampliier (lt ? 1431) combina - tion. the fb pin is connected to gnd, forcing comp high. the collector of the optoisolator is connected to comp directly. the voltage comp is internally attenuated by the ltc3722-1. the attenuated comp voltage provides one input to the phase modulation comparator. this is the current command. the other input to the phase modula - tion comparator is the ramp voltage, level shifted by approximately 650mv. this is the current loop feedback. during every switching cycle, alternate diagonal switches (ma-md or mb-mc) conduct and cause current in an output inductor to increase. this current is seen on the primary of the power transformer divided by the turns ratio. since the current sense resistor is connected between gnd and th e two bottom bridge transistors, a voltage proportional to the output inductor current will be seen across r sense . the high side of r sense is also connected to cs, usually through a small resistor (r slope ). when the voltage on cs exceeds either (comp/4.3) C650mv, or 300mv, the overlap conduction period will terminate. during normal operation, the attenuated comp voltage will determine the cs trip point. during start-up, or slewing conditions following a large load step, the 300mv cs threshold will terminate the cycle, as comp will be driven high, such that the attenuated version exceeds the 300mv threshold. in extreme conditions, the 650mv threshold on cs will be exceeded, invoking a soft-start/restart cycle. selecting the power stage components perhaps the most critical part of the overall design of the converter is selecting the power mosfets, transformer, inductors and ilter capacitors. tremendous gains in ef - iciency, transient performance and overall operation can be obtained as long as a few simple guidelines are followed with the phase-shifted full bridge topology. operation figure 12. phase modulation circuitry (ltc3722-1) 650mv 12a 372212 f12 r s q r sq + C + C + C + C qq c b d a clk clk clk 1.2v v ref soft-start amplifier ideal erroramplifier toggle f/f phase modulation logic phase modulation comparator fromcurrent limit comparator blanking fb comp ss r leb cs 14.9k 50k downloaded from: http:///
ltc3722-1/ltc3722-2 22 372212fb for more information www.linear.com/ltc3722 power transformer switching frequency, core material characteristics, series resistance and input/output voltages all play an important role in transformer selection. close attention also needs to be paid to leakage and magnetizing inductances as they play an important role in how well the converter will achieve zvs. planar magnetics are very well suited to these applications because of their excellent control of these parameters. turns ratio the required turns ratio for a current doubler secondary is given below. depending on the magnetics selected, this value may need to be reduced slightly. turns ratio formula: n = v in(min) ? d max 2 ? v out where: v in(min) = minimum v in for operation d max = maximum duty cycle of controller (dc max ) output capacitorsoutput capacitor selection has a dramatic impact on ripple voltage, dynamic response to transients and stability. capacitor esr along with output inductor ripple current will determine the peak-to-peak voltage ripple on the out - put. the current doubler coniguration is advantageous because it has inherent ripple current reduction. the dual output inductors deliver current to the output capacitor 180 degrees out-of-phase, in effect, partially canceling each others ripple current. this reduction is maximized at high duty cycle and decreases as the duty cycle reduces. this means that a current doubler converter requires less output capacitance for the same performance as a conventional converter. by determining the minimum duty cycle for the converter, worse-case v out ripple can be derived by the following formula: v oripple = i ripple ? esr = v o ? esr l o ? 2 ? f sw (1C d)(1C 2d) operation where:d = minimum duty cycle f sw = oscillator frequency l o = output inductance esr = output capacitor series resistance the amount of bulk capacitance required is usually system dependent, but has some relationship to output inductance value, switching frequency, load power and dynamic load characteristics. polymer electrolytic capacitors are the preferred choice for their combination of low esr, small size and high reliability. for less demanding applications, or those not constrained by size, aluminum electrolytic capacitors are commonly applied. most dc/dc convert - ers in the 100khz to 300khz range use 20f to 25f of bulk capacitance per watt of output power. converters switching at higher frequencies can usually use less bulk capacitance. in systems where dynamic response is critical, additional high frequency capacitors, such as ceramics, can substantially reduce voltage transients. power mosfets the full bridge power mosfets should be selected for their r ds(on) and bv dss ratings. select the lowest bv dss rated mosfet available for a given input voltage range leaving at least a 20% voltage margin. conduction losses are directly proportional to r ds(on) . since the full bridge has two mosfets in the power path most of the time, conduction losses are approximately equal to: 2 ? r ds(on) ? i 2 , where i = i o 2n switching losses in the mosfets are dominated by the power required to charge their gates, and turn-on and turn-off losses. at higher power levels, gate charge power is seldom a signiicant contributor to eficiency loss. zvs operation virtually eliminates turn-on losses. turn-off losses are reduced by the use of an external drain to source snubber capacitor and/or a very low resistance turn-off driver. if synchronous rectiier mosfets are used on the secondary, the same general guidelines apply. keep in mind, however, that the bv dss rating needed for these can be greater than v in(max) /n, depending on how well the downloaded from: http:///
ltc3722-1/ltc3722-2 23 372212fb for more information www.linear.com/ltc3722 operation secondary is snubbed. without snubbing, the secondary vol tage can ring to levels far beyond what is expected due to the resonant tank circuit formed between the secondary leakage inductance and the c oss (output capacitance) of the synchronous rectiier mosfets. switching frequency selection unless constrained by other system requirements, the power converters switching frequency is usually set as high as possible while staying within the desired eficiency target. the beneits of higher switching frequencies are many including smaller size, weight and reduced bulk capacitance. in the full bridge phase-shift converter, these principles are generally the same with the added complica - tion of maintaining zero voltage transitions, and therefore, higher eficiency. zvs is achieved in a inite time during the switching cycle. during the zvs time, power is not delivered to the output; the act of zvs reduces the maxi - mum available duty cycle. this reduction is proportional to maximum output power since the parasitic capacitive element (mosfets) that increase zvs time get larger as power levels increase. this implies an inverse relationship between output power level and switching frequency. table 1 displays recommended maximum switching frequency vs power level for a 30v/75v in to 3.3v/5v out converter. higher switching frequencies can be used if the input voltage range is limited, the output voltage is lower and/or lower eficiency can be tolerated. table 1. switching frequency vs power level <50w 600khz <100w 450khz <200w 300khz <500w 200khz <1kw 150khz <2kw 100khz closing the feedback loopclosing the feedback loop with the full bridge converter involves identifying where the power stage and other system poles/zeroes are located and then designing a com - pensation network around the converters error ampliier to shape the frequency response to insure adequate phase margin and transient response. additional modiications will sometimes be required in order to deal with parasitic elements within the converter that can alter the feedback response. the compensation network will vary depending on the load current range and the type of output capacitors used. in isolated applications, the compensation network is generally located on the secondary side of the power supply, around the error ampliier of the opto-coupler driver, usually an lt1431 or equivalent. in nonisolated systems, the compensation network is located around the ltc3722-1/ltc3722-2s error ampliier. in current mode control, the dominant system pole is determined by the load resistance (v o /i o ) and the output capacitor 1/(2 ? r o ? c o ). the output capacitors esr 1/(2 ? esr ? c o ) introduces a zero. excellent dc line and load regulation can be obtained if there is high loop gain at dc. this requires an integrator type of compensator around the error ampliier. a procedure is provided for deriving the required compensation components. more complex types of compensation networks can be used to obtain higher bandwidth if necessary. step 1. calculate location of minimum and maximum output pole: f p1(min) = 1 (2 ? r o(max) ? c o ) f p1(max) = 1 (2 ? r o(min) ? c o ) step 2. calculate esr zero location: f z1 = 1 (2 ? r esr ? c o ) step 3. calculate the feedback divider gain: r b (r b + r t ) or v ref v out if polymer electrolytic output capacitors are used, the esr zero can be employed in the overall loop compensation and optimum bandwidth can be achieved. if aluminum electrolytics are used, the loop will need to be rolled off prior to the esr zero frequency, making the loop response slower. a linearized spice macromodel of the control downloaded from: http:///
ltc3722-1/ltc3722-2 24 372212fb for more information www.linear.com/ltc3722 loop is very helpful tool to quickly evaluate the frequency response of various compensation networks. polymer electrolytic (see figure 13) 1/(2c c r i ) sets a low frequency pole. 1/(2c c r f ) sets the low frequency zero. the zero frequency should coincide with the worst- case lowest output pole frequency. the pole frequency and mid frequency gain (r f /r i ) should be set such so that the loop crosses over zero db with a C1 slope at a frequency lower than (f sw / 8). use a bode plot to graphi - cally display the frequency response. an optional higher frequency pole set by cp2 and r f is used to attenuate switching frequency noise. aluminum electrolytic (see figure 13) the goal of this compensator will be to cross over the output minimum pole frequency. set a low frequency pole with c c and r in at a frequency that will cross over the loop at the output pole minimum f, place the zero formed by c c and r f at the output pole f. improve transient response, particularly overshoot, and improve zvs ability at light loads. programming the synchronous recti?er turn-off delay the ltc3722-1/ltc3722-2 controllers include a feature to program the turn-off edge of the secondary side synchro - nous rectiier mosfets relative to the beginning of a new primary side power delivery pulse. this feature provides optimized timing for the synchronous mosfets which improves eficiency. at higher load currents it becomes more advantageous to delay the turn-off of the synchro - nous rectiiers until the transformer core has been reset to begin the new power pulse. this allows for secondary freewheeling current to low through the synchronous mosfet channel instead of its body diode. the turn-off delay is programmed with a resistor from sprg to gnd (see figure 14). the nominal regulated voltage on sprg is 2v. the external resistor programs a current which lows out of sprg. the delay can be adjusted from approximately 20ns to 200ns, with resistor values of 10k to 200k. do not leave sprg loating. the amount of delay can also be modulated based on an external current source that sinks current out of sprg. care must be taken to limit the current out of sprg to 350a or less. figure 14. synchronous delay circuitry figure 13. compensation for polymer electrolytic + C 2.5v r f r l r d esr ref r i c c c o c p2 v out coll comp opto v out lt1431 or equivalent precision error amp and reference optional 372212 f13 C + turn-off sync out 372212 f14 + C v 2v sprg r sprg synchronous recti?cation the ltc3722-1/ltc3722-2 produces the precise timing signals necessary to control current doubler secondary side synchronous mosfets on oute and outf. synchronous rectiiers are used in place of schottky or silicon diodes on the secondary side of the power supply. as mosfet r ds(on) levels continue to drop, signiicant eficiency im - provements can be realized with synchronous rectiication, provided that the mosfet switch timing is optimized. an additional beneit realized with synchronous rectiiers is bipolar output current capability. these characteristics current doubler the current doubler secondary employs two output induc - tors that equally share the output load current. the trans - former secondary is not center-tapped. this coniguration provides 2x higher output current capability compared to similarly sized single output inductor modules, hence the name. each output inductor is twice the inductance value as the equivalent single inductor coniguration and the transformer turns ratio is one-half that of a single inductor operation downloaded from: http:///
ltc3722-1/ltc3722-2 25 372212fb for more information www.linear.com/ltc3722 secondary. the drive to the inductors is 180 degrees out- of-phase which provides partial ripple current cancellation in the output capacitor(s). reduced capacitor ripple current lowers output voltage ripple and enhances the capacitorss reliability. the amount of ripple cancellation is related to duty cycle (see figure 15). although the current doubler requires an additional inductor, the inductor core volume is proportional to li 2 , thus the size penalty is small. the transformer construction is simpliied without a center-tap winding and the turns ratio is reduced by one-half compared to a conventional full wave rectiier coniguration. synchronous rectiication of the current doubler second - ary requires two ground referenced n-channel mosfets. the timing of the ltc3722-1/ltc3722-2 drive signals is shown in the timing diagram. full bridge gate drive the full bridge converter requires high current mosfet gate driver circuitry for two ground referenced switches and two high side referred switches. providing drive to the ground referenced switches is not too dificult as long as the traces from the gate driver chip or buffer to the gate and source leads are short and direct. drive requirements are further eased since all of the switches turn on with zero vds, eliminating the miller effect. low turn-off resistance is critical, however, in order to prevent excessive turn-off losses resulting from the same miller effects that were not an issue for turn-on. the ltc3722-1/ltc3722-2 does not require the propagation delays of the high and low side drive circuits to be precisely matched as the directsense zvs circuitry will adapt accordingly. as a result, ltc3722-1/ ltc3722-2 can drive a simple npn-pnp buffer or a gate driver chip like the ltc1693-1 to provide the low side gate drive. providing drive to the high side presents additional challenges since the mosfet gate must be driven above the input supply. a simple circuit (figure 17) using a single ltc1693-1, an inexpensive signal transformer and a few discrete components provides both high side gate drives (a and c) reliably. the ltc4440 high side driver can also be applied. the ltc4440 eliminates the signal transformer and is preferred for applications where v in is less than 80v (max). figure 15. ripple current cancellation vs duty cycle 10 0 0.25 0.5 duty cycle normalized output ripple current attenuation 3722212 f15 note: inductor(s) duty cycle is limited to 50% with current doubler phase shift control. figure 17. high side gate driver circuitry figure 16. isolated drive circuitry in1 out1 in2 out2 2:1:1 oute outf ltc3722 gnd1gnd2 ltc1693-1 372212 f16 in out outa or outc gnd 1/2 ltc1693-1 372212 f17 v cc 0.1f 2fcer 0.1f signal transformer 2k bat 54 bridgeleg regulated bias powermosfet v in ltc3722 operation downloaded from: http:///
ltc3722-1/ltc3722-2 26 372212fb for more information www.linear.com/ltc3722 package description .337 C .344* (8.560 C 8.738) gn24 rev b 0212? 1 2 3 4 5 6 7 8 9 10 11 12 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 17 18 19 20 21 22 23 24 15 14 13 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .0075 C .0098 (0.19 C 0.25) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b) downloaded from: http:///
ltc3722-1/ltc3722-2 27 372212fb for more information www.linear.com/ltc3722 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 03/10 i-grade parts added. relected throughout the data sheet. 1 to 28 b 02/13 h-grade part added. relected throughout the data sheet. 1 to 28 downloaded from: http:///
ltc3722-1/ltc3722-2 28 372212fb for more information www.linear.com/ltc3722 ? linear technology corporation 2009 lt 0213 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3722 part number description comments ltc3723-1/ltc3723-2 synchronous push-pull and full-bridge controllers high eficiency with on-chip mosfet drivers ltc3721-1 non-synchronous push-pull and full-bridge controller minimizes external components, on-chip mosfet drivers ltc3765/ltc3766 isolated synchronous forward controller chip set ideal for 24v or 48v input applications lt1952/lt1952-1 isolated synchronous forward controllers ideal for 24v or 48v input applications ltc3901 secondary-side synchronous driver for full-bridge and push-pull converters programmable timeout, reverse inductor current sense ltc4440 high voltage high side mosfet driver 100v, 2.4a pull-up, 1.6 pull-down, sot-23 and msop-8 packages related parts typical application 1k 16 1 adly 20k 4.99k 150 ? pdly outb outd v ref dprg nc sync sprg ct r leb fb gnd pgnd ss cs 11 14 1 24 13 5 6 23 22 7 4 3 2 8 9 20 1018 12 17 outf oute 15 16 18 45 150k 5v ref sbusv cc uvlo 0.47f 20k 1/4w 12v v in 220pf 1 f 220pf 30.1k 182k comp ltc3722-1 b d q2 4 2 3 8 1 6 d3 d5 d4 12v 7 q4 12v d Cv out Cv out Cv out i sns 1.10k 0.02 ? 1.5w 0.02 ? 1.5w 13k 1/2w d1d6 372212 ta02 +v out si7852dp 4 si7852dp 2 q1q3 12v b si7852dp 2 si7852dp 2 si7852dp 4 +v out 12v35a +v out c1, c2180 f 16v 2 0.47 f 100v 12v 100 ? d9 3.3v l4 1mh l2 150nh l1, 1.3h v in 36v to 72v +v in Cv in d7 1 6 t2 5:5(105 h):1:1 t1 5:5(105 h):1:1 7 8 2 4 2 4 10 11 7 8 10 11 22 ? 0.1 f t3 1(1.5mh):0.5 outa 21 a outc 19 c c3 68f 20v 0.22f d8 1 1 7 6 5 7 8 6 5 2 3 4 2 750 ? 200k 330 ? moc207 5.1k 220pf 10k 33k 8.25k d11 100k 180pf 2.2nf 330pf 22nf 68nf c4 2.2nf 250v i sns 5v ref 0.047f 220pf d125.1v v + comp r top gndf gnds r mid coll cse + 6 cse C 5 me 2 8 4 10 13 330pf 1f 1f 7 4.02k 2.15k me2 3 sycn ref 820pf200v 15 ? 1.5w 1f lt1431 v cc gnd gnd ts in tg c boost 2.7k 9.53k 10k 2.49k Cv out 470 ? 1/4w 4.64k 1/4w 100 ? 0.47 f, 100v = tdk c3216x7r2a474m 1 f, 100v = tdk c4532x7r2a105m c1, c2: sanyo 16sp180m c3: avx tpse686m020r0150 c4: murata de2e3kh222mb3b d1, d4, d5, d6: murs120t3 d2, d3, d7, d8: bas21 d9: mmbz5226b d10: mmbz5240b d11: bat54 d12: mmbz5231b l1: sumida cdep105-1r3mc-50 l2: pulse pa0651 l3: pa1294.910 l4: coilcraft do1608c-105 q1, q2: zetex fmmt619 q3, q4: zetex fmmt718 t1, t2: pulse pa0526 t3: pulse pa0785 ? v high l3 0.85 h ? ? ? ? ? 0.47 f 100v 4 2 3 8 1 6 d2 12v 7 si7852dp 2 0.22f v cc gnd gnd ts in tg a boost ltc4440ems8e ltc4440ems8e 1f 100v 1f 100v 4 ? + v high ? + 512w 51 ? , 2w 0.47f 100v csf + ltc3901egn gnd pgnd gnd2 pgnd2 timer pv cc 11 csf C 12 mf 14 4.02k 2.15k mf2 v cc 15 4.64k 1/4w 30 . 1k 100 ? d10 10v +v out mmbt3904 1m mmbt3904 ltc3722/ltc4440 420w, 36v-72v input to 12v/35a isolated full bridge supply downloaded from: http:///

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